The present invention relates to a capacitive load driving circuit having an input selection circuit and a liquid crystal display device using the capacitive load driving circuit, and more particularly to an improved capacitive load driving circuit in which an input voltage range is extended.
Generally, as shown in FIG. 1, a liquid crystal display device comprises a liquid crystal display 1 in which a plurality of liquid crystal cells are arranged in a matrix shape, a liquid crystal display driving circuit 2 for supplying a video signal to the liquid crystal display 1 through a plurality of signal lines 3, and a scanning line selecting circuit 4 for selectively driving a plurality of scanning lines 5. The liquid crystal display 1 comprises a plurality of liquid crystal cells 6 which are arranged in a matrix shape including a first direction of the signal lines 3 and a second direction of the scanning lines 5, both the directions which are intersected in a right angle, namely, liquid crystal cells 6aa-6mn of "m.times.n" are provided and include m-th cells in the direction of the signal lines and n-th cells in the line of the scanning line.
The signal line 3 includes n-th signal lines 3a-3n each for supplying the video signal to the liquid crystal cells in the column direction, and the scanning line 5 includes m-th scanning line 5a-5m each for supplying the selection signal to the liquid crystal cells in the row direction. Accordingly, for example, the signal line 3a corresponds to the liquid crystal cells 6aa, 6ba, 6ca, . . . , 6(m-2)a, 6(m-1)a and 6ma in the column direction, and the scanning line 5a corresponds to the liquid crystal cells 6aa, 6ab, 6ac, . . . , 6a(n-2), 6a(n-1) and 6an in the row direction.
FIG. 2 shows an example of a general configuration of the display driving circuit 2 shown in FIG. 1. In FIG. 2, the display driving circuit 2 comprises a shift register 7 as sampling pulse transfer means, a selection signal line 8 including first and second selection signal lines 8aand 8b for supplying first and second selection signals SEL1 and SEL2, an AND circuit 9 for calculating a logical product between a sampling pulse and the selection signal, sample and hold circuits 10 having twice as many numbers as pixels necessary to on horizontal scanning line have, first and second switch groups 13 and 14 for selecting outputs of the sample and hold circuits 10 under a holding condition by the first and second selection signals SEL1 and SEL2, and buffer circuits 15 for driving the liquid crystal display 1 (FIG. 1) by a selected signal.
Since the second selection signal line 8b includes an inverting logic circuit (inverter) 8A, the second selection signal SEL2 in the signal line 8b is a signal which is generated by inverting the first selection signal SEL1 and has a level different from that of the first selection signal SEL1.
The AND circuit 9 includes AND circuits 9a1, 9b1, . . . , and 9n1 on one side for obtaining a logical product (an AND function) between the first selection signal SEL1 and the sampling pulse supplied from the shift register 7, and AND circuits 9a2, 9b2, . . . , and 9n2 on the other side for obtaining a logical product between the sampling pulse and the second selection signal.
Each of the sample and hold circuits 10 comprises a switch 11 for sampling the video signal to the liquid crystal display by a output of the AND circuit, and a capacitor 12 for holding the video signal of one horizontal scanning period, and the circuit 10 includes a plurality of sample and hold circuits 10a1, 110a2, 10b1, 10b2, . . . , 10n1, and 10n2 respectively corresponding to the AND circuits 9a1, 9a2, 9b1, 9b2, . . . , 9n1, and 9n2.
Outputs of the sample and hold circuits 10a1, 10b1, . . . , and 10n1 are supplied to switches 13a, 13b, . . . , and 13n which are turned on or off by the first selection signal SEL1, and outputs of the sample and hold circuits 10a2, 10b2, . . . , and 10n2 are supplied to switches 14a, 14b, and 14n which are turned on or off by the second selection signal SEL2.
The buffer circuit 15 includes a buffer circuit 15a to which the video signal is supplied through the switches 13a and 14a, a buffer circuit 15b to which the video signal is supplied through the switches 13b and 14b, as the same as above to a buffer in to which the video signal is supplied through the switches 13n and 14n. Outputs of the buffer circuits 15a, 15b, . . . , and 15n are supplied to each of cells in the liquid crystal display 1 through the signal lines 3a, 3b, . . . , 3n.
When an output signal of the selectively selected sample and hold circuit 10 is outputted through the buffer circuit 15, if the signal source has a low impedance, a simple switch circuit just selects an output signal of the sample and hold circuit. However, when the output of the sample and hold circuit is an input signal to the buffer circuit 15 through the switch 13 or 14 as shown in FIG. 3, the selection signals SEL1 and SEL2 impressed to the switches leaks out through parasitic capacitance 13A, 13B, 14A and 14B, thereby resulting the problem to generate an error in a held value. Furthermore, when the switches 13 and 14 is formed of a metal oxide semiconductor (MOS) field effect transistor (FET), channel charges of the MOS FET become a cause by adding with a holding capacitance 12 of the sample and hold circuit 10. Accordingly, in the case where the buffer circuit 15 having such switches 13 and 14 is used in the liquid crystal display driving circuit, errors occurring in the switch circuits make the picture quality to be deteriorated.
In FIG. 3, since a signal component held in the sample and hold circuit remains as charges in capacitance such as a wiring capacitance 16A from the switch circuits 13 and 14 to the buffer circuit 15 and an input capacitance 16B of the buffer circuit 15, after any output is selected by the switches 13 or 14, the output is interposed over the charges of the signal component which remain in the wiring capacitance 16A and the input capacitance 16B of the buffer circuit 15 in the past sampling, thereby resulting that the signal in the past sampling leaks out from the scanning line to the next scanning line on the liquid crystal display.
In order to avoid the above condition, the conventional device performs an impedance conversion by inserting source followers 17 and 18 before the selecting switches 13 and 14 as shown in FIG. 4. In FIG. 4, the output buffer portion 15 comprises a voltage follower having a similar source follower 19 which is provided on a negative feedback path to compensate a level shift by a gate-source voltage caused by the source followers 17 and 18 (refer to a detailed circuit diagram shown in FIG. 5).
In FIG. 5, the source follower 17 comprises a metal oxide semiconductor field effect transistor (MOS FET) M1 having a gate to which the first input signal INPUT1 is supplied, and a current source I1. A first switch 20 receives a source potential of the MOS FET Mi.
The source follower 18 comprises a MOS FET M2 having a gate to which the second input signal INPUT2 is supplied, and a current source I2, and a source potential of the MOS FET M2 is supplied to the second switch 14.
The buffer circuit 15 comprises a differential amplifier portion and an inverting amplifier portion, and the differential amplifier portion comprises a current source I3, a P-channel MOS FET M3 having a gate to which an output from the switch 13 or 14 is supplied, a P-channel MOS FET M4 constituting a differential pair with the MOS FET M3 and having a gate to which an output of a source follower 19 is supplied, and N-channel MOS FET M5 and M6 which are connected to the MOS FET M3 and M4, respectively, and having gates which are interconnected with each other. The inverting amplifier portion comprises a current source I4 and a N-channel MOS FET M7, and a drain potential of the MOS FET M7 is supplied to the liquid crystal display as an output signal OUTPUT and fed back to the source follower 19.
The source follower 19 comprises an N-channel MOS FET M8 having a gate to which a drain potential of the MOS FET M& is supplied, and a current source I5, and a source potential of the MOS FET M8 is fed back to a gate of the MOS FET M4.
However, since such above-mentioned method can not normally operate unless a voltage range of the input signals INPUT1 and INPUT2 is more than a threshold voltage V.sub.th of the N-channel MOS FET constituting the source follower when the source followers 17, 18 and 19 shown in FIG. 4 are constituted from the N-channel MOS FET, respectively, there is a problem that an effective voltage range of the input signals is limited. Accordingly, if the buffer circuit having the selection switches is applied to the liquid crystal driving circuit, it is necessary to provide a power source voltage at least more than the threshold voltage of the N-channel MOS FET because of an amplitude of the signal, thereby resulting a problem that power consumption increases.